This code will take a four bit number and decode it into the seven individual segments to drive a seven segment display. nIn is the four bit number to be decoded and ssOut is the array of segments for the display going from a, being the LSB, to g being the MSB.
Change Log:
11/1/2010: Added default case statement to prevent possible latching.
Just wanna try the code….do you have the test bench? tq
You should add a default case and set the value the outputs to some arbitrary values. otherwise it may synthesize to an unintentional latch.
Thanks, mate – I’ve been coding one of these to be a poor-man’s logic analyser using a Xilinx CPLD. Was driving myself crazy trying to do it from scratch using NAND gates, thought it *must* be easier with a simple if/else|switch – and you have proved that it is so. One for my Library of Handy Verilog Snippets.
Sweet! This definitely helped me with my homework, thanks a ton 😀
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can i have the .ucf file for the above code for dumping into spartan 3e series….
This example would be what you need to add to a ucf file if you were to use the Digilent PmodSSD, a dual seven segment display, and connect it to J1 & J2 of a Spartan 3E Starter Kit. To use this with a different port or on your own custom board all you would need to do is change the LOC = “…” to what ever IO pins you plan on using.
NET "nIn<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "nIn<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "nIn<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "nIn<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
#NET "ssOut<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "ssOut<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "ssOut<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "ssOut<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "ssOut<4>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "ssOut<5>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "ssOut<6>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
It is helpful to guide my Assignment .. thanks
how that 4 bit number is provided? I am confused..how the value of nIn is given?
Zakee,
I think this will answer your question.
The input iIn is given as a 4-bit binary number. With a 4-bit binary number you can represent values from 0 to 15, these values are typicality show in hexadecimal using a combination of 0 through 9 and A through F ie: 0, 1, 2, … 8, 9, A, B, … E, F. By using this module connected up to a seven segment display, the display will show the number or letter that is represented by the 4-bit binary number.
excelente!! thanks for your reply..
How can i design a decoder for two digit? I mean if i want to count from 00 to FF and see it in my seven segment?
There are two ways in which this can be accomplished. Given that you have a 8-bit number you can take two of the seven segment display decoder modules above and attach bits 7 through 4 to one module and bits 3 through 0 to another module. Then attach the outputs of these to two individual seven segment displays. They second way and more compact way would be to feed the 8-bit number into a dual seven segment display decoder and connect the output of the module to display like this, along with a clock going to the clock input of the module and the CAT pin on the display.
I tried it. It didn’t worked. All I can see in my display is count like 00, 11, 22, 33 till FF. Rather i want to see count like 00, 01, 02, 03 till FF.
@daniel : can you give me your email id, I can forward you my code or I can post here. Whatever suits you.
code worked..thanks !!!
hello i am been working for a project with i want to display 00 01, 02 ,,,,, but i can only get . 00, 11, 22, 33 till FF. i wish you can help me my email is odnava@hotmail.com
i would like to help me with this problem
thank you
Oskar, how is your circuit setup? Typically you would enable one seven-segment display at a time while sending the number you want to display at the same time, then switch to the second one while sending the number for that one. Also take a look at my dual seven segment display decoder post, it might help you out.
Is there a way to use this code having the seven segment display display the decimal values of the input?
Mario, you would need to put the binary number into a binary-coded decimal (BCD) decoder. This will break up the binary encoded number into multiple four-bit BCD numbers, ranging from 0 to 9, one for each decimal place ie: ones, tens, hundreds, and so on. Then you can feed each of the BCD numbers into a seven segment decoder and then drive an LED display. This will make a good post, so give me a day or two and I will probably have some BCD decoder code posted.
Pingback: Binary to Binary-Coded Decimal (BCD) Converter | Death by Logic
can you help me !!! I have a project in a verilog and i feel it’s hard to do with my self
I would suggest asking a forum, you will get a quicker response and greater variety of help with your project. A few suggestions would be:
http://www.edaboard.com/group128.html
https://groups.google.com/forum/m/#!forum/comp.lang.verilog
http://embdev.net/forum/fpga-vhdl-verilog
for active low:
case(n)
4’h0: ssOut = 7’b1000000;
4’h1: ssOut = 7’b1111001;
4’h2: ssOut = 7’b0100100;
4’h3: ssOut = 7’b0110000;
4’h4: ssOut = 7’b0011001;
4’h5: ssOut = 7’b0010010;
4’h6: ssOut = 7’b0000010;
4’h7: ssOut = 7’b1111000;
4’h8: ssOut = 7’b0000000;
4’h9: ssOut = 7’b0011000;
4’hA: ssOut = 7’b0001000;
4’hB: ssOut = 7’b0000011;
4’hC: ssOut = 7’b1000110;
4’hD: ssOut = 7’b0100001;
4’hE: ssOut = 7’b0000110;
4’hF: ssOut = 7’b0001110;
default: ssOut = 7’b0110110;
endcase