Binary to Binary-Coded Decimal (BCD) Converter

A binary to binary-coded decimal, or BCD for short, is a method storing decimal numbers in binary form. The majority of the time a number in a logic design is stored as a binary number internally as to simplify math and logic operations and converted to a set of BCD numbers only when it needs to then be sent to something that requires it in decimal number form i.e. a display of some sort. The Verilog and VHDL code below is for an 8-bit binary to BCD decoder that gives and ones, tens and hundreds decimal place output for driving a display or other device. Continue reading

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1’s or 0’s Counter

This little bit of code will count the number of 1’s or 0’s, depending on how it is configured, in the input signal. This module is not the most efficient way to program one of these, when it comes to synthesizing, but when dealing with variable length I/O it is the easiest. The INPUT_WIDTH variable determines how wide the input signal is and the COUNT_WIDTH does the same for the count signal. The COUNT_TYPE determines if you are counting the number of 1’s or 0’s. Every time the write enable (WrEn) is high on the rising edge of a clock pulse the module will count the number of 1’s of 0’s on the input signal and write the result to the count signal.
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Verilog: n-Bit Up Counter

This is a simple n-bit wrapping up counter. The n parameter can be changed to make this 4, 8, … bit counter were n = <number of bits> – 1. The CLK signal can be any signal you want and will increment the value of the counter on the positive edge of a pulse, RST is the negative edge reset signal which will reset the counter to 0 or any number of your choosing also be sure to change the initial value, which is the starting value when the module initialized. The output count is the current value of the counter. Continue reading

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Verilog: Dual Seven Segment Display Driver

This is an expansion upon my SevenSegmentDisplayDriver module which will allow you to drive a dual seven segment display, specifically the add-on for the Spartan 3E but it should be quite easy to modify for other FPGA’s. The basic premise of this module is you have a dual seven segment display which activates the left or right display depending on whether the enable signal is high or low. So using the code below, when the clock signal is low (right display is active) we send the lower four bits of our number to the display so they show on the right hand side display. When the clock is high (left display is active) we send the upper four bit to the left hand display. By doing this a few hundred times a second both numbers apear be on the display at once. To use this module you must slow down the clock to an appropriate rate and assign it to the enable pin for the display and the CLK input on this module. bIn in the 8-bit number you wish to display and ssOut is the array of segments for the seven segment display (See the SevenSegmentDisplayDriver post for more details) Continue reading

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Verilog: n-Bit Adder

This is code is for an simple asynchronous wrapping n-bit adder. By changing the value of n you can make it a 2, 4, … bit adder where n = <number of bits> – 1. f is the output register that will have the current value of the counter, cOut is the carry output. a & b are the number inputs and cIn is the carry input. Both the number outputs and inputs are set by the value of n so you can add two n-bit numbers and a carry bit then get an n-bit number plus carry bit out. Continue reading

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