Verilog: Dual Seven Segment Display Driver

This is an expansion upon my SevenSegmentDisplayDriver module which will allow you to drive a dual seven segment display, specifically the add-on for the Spartan 3E but it should be quite easy to modify for other FPGA’s. The basic premise of this module is you have a dual seven segment display which activates the left or right display depending on whether the enable signal is high or low. So using the code below, when the clock signal is low (right display is active) we send the lower four bits of our number to the display so they show on the right hand side display. When the clock is high (left display is active) we send the upper four bit to the left hand display. By doing this a few hundred times a second both numbers apear be on the display at once. To use this module you must slow down the clock to an appropriate rate and assign it to the enable pin for the display and the CLK input on this module. bIn in the 8-bit number you wish to display and ssOut is the array of segments for the seven segment display (See the SevenSegmentDisplayDriver post for more details) Continue reading