Visualizing the tension on wire for a suspended mass with python

I’ve been playing around with the idea of building a rig to suspend an object, like a camera or prop, using three wires and then control its position in 3-D space using a few stepper motors and a micro-controller. The general idea is similar to the skycam system they use at football games and other pro sports, or a large scale delta robot. The first thing I needed to figure out was how much I wanted this rig to be able to hold and how much tension (force) would be required to hold and move this weight around. Additional I wanted to be able to visualize the results so I could look for any peaks, valleys or other anomalies that would throw off my calculations. I ended up writing the python script below utilizing the mpmath, sympy and matplotlib libraries to calculate the tension on a wire due to a suspend mass at a specific height and plot it as the weight moves around the x/y plane. The image below is a sample of the output from this script for a 5 kg mass suspend 2.0 m above the ground with three anchor points at 3.0 m above ground level and each 120 degrees apart.

wire_tension_plot

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Binary to Binary-Coded Decimal (BCD) Converter

A binary to binary-coded decimal, or BCD for short, is a method storing decimal numbers in binary form. The majority of the time a number in a logic design is stored as a binary number internally as to simplify math and logic operations and converted to a set of BCD numbers only when it needs to then be sent to something that requires it in decimal number form i.e. a display of some sort. The Verilog and VHDL code below is for an 8-bit binary to BCD decoder that gives and ones, tens and hundreds decimal place output for driving a display or other device. Continue reading

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BeagleIO

I’ve been working on a c library to simplify access to the gpio on the BeagleBone board for use with the robot I am working on. My initial pass at this worked decently but was not as flexible as I had hoped. Over the past week or so I’ve been re-writing the majority of the code as a base class and set of derived classes to handle the various pin functions. So far I have objects to handle accessing analog pins, basic digital gpio I/O, and serial ports. The results of my work can be found at: http://code.google.com/p/beagleio/source/browse/branches.

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VHDL: Standard FIFO

FIFOs (First In, First Out) are essentially memory buffers used to temporarily store data until another process is ready to read it. As their name suggests the first byte written into a FIFO will be the first one to appear on the output. Typically FIFOs are used when you have two processes that operate and a different rate. A common example is a high speed communications channel that writes a burst of data into a FIFO and then a slower communications channel that read the data as need to send it at a slower rate.

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BealgeBone unexport gpio script

This is a simple bash script, that took way to long to get correct, to unexport all the of exported gpio pins on your BeagleBone board at once.

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VHDL: RAM

RAM is a useful thing to have when you need to store bits of information for later, the code below is for a simple, single port write first, RAM module and test bench. This may seem like a great bit of code to have lying around, but in reality it’s more for educational purposes. If you were actually going to use a RAM module like the one below you should really use a RAM generator from the manufacture of what ever device you are using ie: Xilinx, Altera, Lattice… These generated module are designed to take advantage of special RAM blocks built into the FPGA which allows them to be fast and efficient. Continue reading

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October 2012 site update

This weekend I have spent some time and updated the site, the most obvious will be the new theme. The banner photo is a shot of my home workbench which is currently occupied by one of my robots. I have also gone through and cleaned up the tags and categories along with adding a list of categories to the side bar.

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1’s or 0’s Counter

This little bit of code will count the number of 1’s or 0’s, depending on how it is configured, in the input signal. This module is not the most efficient way to program one of these, when it comes to synthesizing, but when dealing with variable length I/O it is the easiest. The INPUT_WIDTH variable determines how wide the input signal is and the COUNT_WIDTH does the same for the count signal. The COUNT_TYPE determines if you are counting the number of 1’s or 0’s. Every time the write enable (WrEn) is high on the rising edge of a clock pulse the module will count the number of 1’s of 0’s on the input signal and write the result to the count signal.
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VHDL: Debounce

This module is a simple debounce that will prevent switch noise from entering logic and causing havoc. It works by initially latching the input twice for synchronization between the (asynchronous) real world and the (synchronous) logic. The input is then sampled eight times, one every 50,000 clock cycles, and only after there have been eight consecutive samples of all the same reading, high or low, does the input change. This process happens continuously so whenever there in a change in the input that is steady the output will follow. With a clock of 50 MHz the samples will take place every millisecond giving a delay of 8 milliseconds, this can be adjusted for a specific time or period by changing the value of Delay. Continue reading

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