VHDL: RAM

RAM is a useful thing to have when you need to store bits of information for later, the code below is for a simple, single port write first, RAM module and test bench. This may seem like a great bit of code to have lying around, but in reality it’s more for educational purposes. If you were actually going to use a RAM module like the one below you should really use a RAM generator from the manufacture of what ever device you are using ie: Xilinx, Altera, Lattice… These generated module are designed to take advantage of special RAM blocks built into the FPGA which allows them to be fast and efficient. Continue reading

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1’s or 0’s Counter

This little bit of code will count the number of 1’s or 0’s, depending on how it is configured, in the input signal. This module is not the most efficient way to program one of these, when it comes to synthesizing, but when dealing with variable length I/O it is the easiest. The INPUT_WIDTH variable determines how wide the input signal is and the COUNT_WIDTH does the same for the count signal. The COUNT_TYPE determines if you are counting the number of 1’s or 0’s. Every time the write enable (WrEn) is high on the rising edge of a clock pulse the module will count the number of 1’s of 0’s on the input signal and write the result to the count signal.
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VHDL: Debounce

This module is a simple debounce that will prevent switch noise from entering logic and causing havoc. It works by initially latching the input twice for synchronization between the (asynchronous) real world and the (synchronous) logic. The input is then sampled eight times, one every 50,000 clock cycles, and only after there have been eight consecutive samples of all the same reading, high or low, does the input change. This process happens continuously so whenever there in a change in the input that is steady the output will follow. With a clock of 50 MHz the samples will take place every millisecond giving a delay of 8 milliseconds, this can be adjusted for a specific time or period by changing the value of Delay. Continue reading

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Announcing the ‘Shutter Pod’ project

The goal of the project is to design a timer for SLR cameras capable of taking long exposure and time lapse photography. At the heart of the  device will be a ATmega micro-controller and a 16×2 back lite LCD display. The entire project is being developed as open-source hardware and software being hosted on Google code under the Creative Commons 3.0 BY-SA (share alike, attribution) license for hardware and the GPL version 3 for code. For more information, up to date code and schematics visit http://code.google.com/p/shutterpod.

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BJT Equation Sheet

This is a handy little cheat sheet that I have been working on with equations for common Bi-Junction Transistor (BJT) configurations. It has schematics, DC equations and AC equations for 8 of the most common setups. It  is not quite finished yet but it’s a start so if you find any mistakes or know of stuff I missed please let me know and I will update it.

Update:

The download has been pulled to put the information in a better format and give it an update.

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Notes on using the Robotics Connection I2C line following sensor with Arduino based boards

After many of wasted hours of trying to get the I2C line following sensor from Robotics Connection working with an Arduino based controller board I was finally able to get it to communicate and since there was no other information out there on this issue I decided to write this post. Continue reading

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Verilog: n-Bit Up Counter

This is a simple n-bit wrapping up counter. The n parameter can be changed to make this 4, 8, … bit counter were n = <number of bits> – 1. The CLK signal can be any signal you want and will increment the value of the counter on the positive edge of a pulse, RST is the negative edge reset signal which will reset the counter to 0 or any number of your choosing also be sure to change the initial value, which is the starting value when the module initialized. The output count is the current value of the counter. Continue reading

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Verilog: Dual Seven Segment Display Driver

This is an expansion upon my SevenSegmentDisplayDriver module which will allow you to drive a dual seven segment display, specifically the add-on for the Spartan 3E but it should be quite easy to modify for other FPGA’s. The basic premise of this module is you have a dual seven segment display which activates the left or right display depending on whether the enable signal is high or low. So using the code below, when the clock signal is low (right display is active) we send the lower four bits of our number to the display so they show on the right hand side display. When the clock is high (left display is active) we send the upper four bit to the left hand display. By doing this a few hundred times a second both numbers apear be on the display at once. To use this module you must slow down the clock to an appropriate rate and assign it to the enable pin for the display and the CLK input on this module. bIn in the 8-bit number you wish to display and ssOut is the array of segments for the seven segment display (See the SevenSegmentDisplayDriver post for more details) Continue reading

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Verilog: n-Bit Adder

This is code is for an simple asynchronous wrapping n-bit adder. By changing the value of n you can make it a 2, 4, … bit adder where n = <number of bits> – 1. f is the output register that will have the current value of the counter, cOut is the carry output. a & b are the number inputs and cIn is the carry input. Both the number outputs and inputs are set by the value of n so you can add two n-bit numbers and a carry bit then get an n-bit number plus carry bit out. Continue reading

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