Death by Logic

This module is a simple debounce that will prevent switch noise from entering logic and causing havoc. It works by initially latching the input twice for synchronization between the (asynchronous) real world and the (synchronous) logic. The input is then sampled eight times, one every 50,000 clock cycles, and only after there have been eight [...]

Filed under: Code, FPGA, VHDL by Daniel
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The following code is a simple state machine that determines the direction that the knob on the Spartan 3E is turning and outputs a clock signal (Count) as it turns. A & B are the inputs from the encoders on the knob, RST & CLK are the reset and clock obviously. Count is the clock [...]

Filed under: Code, FPGA, VHDL by Daniel
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