VHDL: Debounce

This module is a simple debounce that will prevent switch noise from entering logic and causing havoc. It works by initially latching the input twice for synchronization between the (asynchronous) real world and the (synchronous) logic. The input is then sampled eight times, one every 50,000 clock cycles, and only after there have been eight [...]

Filed under: Code, FPGA, VHDL by Daniel
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Notes on using the Robotics Connection I2C line following sensor with Arduino based boards

After many of wasted hours of trying to get the I2C line following sensor from Robotics Connection working with an Arduino based controller board I was finally able to get it to communicate and since there was no other information out there on this issue I decided to write this post.

Filed under: Electronics, Hardware, Robotics by Daniel
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Verilog: n-Bit Up Counter

This is a simple n-bit wrapping up counter. The n parameter can be changed to make this 4, 8, … bit counter were n = <number of bits> – 1. The CLK signal can be any signal you want and will increment the value of the counter on the positive edge of a pulse, RST [...]

Filed under: Code, FPGA, Verilog by Daniel
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Verilog: Dual Seven Segment Display Driver

This is an expansion upon my SevenSegmentDisplayDriver module which will allow you to drive a dual seven segment display, specifically the add-on for the Spartan 3E but it should be quite easy to modify for other FPGA’s. The basic premise of this module is you have a dual seven segment display which activates the left [...]

Filed under: Code, FPGA, Verilog by Daniel
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Verilog: Seven Segment Display Decoder

This code will take a four bit number and decode it into the seven individual segments to drive a seven segment display. nIn is the four bit number to be decoded and ssOut is the array of segments for the display going from a, being the LSB, to g being the MSB.

Filed under: Code, FPGA, Verilog by Daniel
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Verilog: n-Bit Adder

This is code is for an simple asynchronous wrapping n-bit adder. By changing the value of n you can make it a 2, 4, … bit adder where n = <number of bits> – 1. f is the output register that will have the current value of the counter, cOut is the carry output. a [...]

Filed under: Code, FPGA, Verilog by Daniel
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State Machine for the Spartan 3E Knob

The following code is a simple state machine that determines the direction that the knob on the Spartan 3E is turning and outputs a clock signal (Count) as it turns. A & B are the inputs from the encoders on the knob, RST & CLK are the reset and clock obviously. Count is the clock [...]

Filed under: Code, FPGA, VHDL by Daniel
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