Category Archives: Hardware

VHDL: First Word Fall Through FIFO

Posted on by
20

In the Standard FIFO post I talked about how a traditional FIFO works and supplied code for one. In this post I will be describing a First Word Fall Through (FWFT) FIFO. The main difference between standard FIFOs and FWFT FIFOs are that, as the name describes, the first byte written into the FIFO immediately appears on the output (See image below). This allows the first byte to be read on the next clock cycle without having to strobe the read enable. Additionally you can read the byte and strobe the write enable high at the same time so the next byte will be available to read on the next clock cycle.
Continue reading →

Share

Daisy Chaining multiple AutoDrivers

Posted on by
1

In a previous post I tested running SPI over a distance of roughly 100 feet using RS-485 over Cat5 with only a single SPI slave device, in this post I will cover the how to have multiple SPI slaves (AutoDriver with RS-485 shield) daisy chained together. The goal here is to communicate with multiple AutoDrivers over a long distance with only a single chip select signal. Continue reading →

Share

AutoDriver SPI over RS-485 Shield v2

Posted on by
Reply

After verifying that the AutoDriver v1 shield was sound, I made a few changes to improve its functionality and ease of use. The biggest change was the addition of a switching power supply that can accept anywhere from 6 to 60 volts. This will allow it to be powered directly from the same power supply used to drive the stepper motors and removes the need for a separate 5v supply. The second change was switching from a transistor to a single logic inverter to invert the chip select signal. During initial testing the transistor would not turn on or off quick enough to function properly, the single logic gate would guarantee the quick switching times needed. The final change was to reorganize the signals on the connector simplify connecting up the wiring between devices.

image

AutoDriver Shield v2 schematic

Continue reading →

Share

SPI over RS-485 Testing

Posted on by
1
Arduino communicating with AutoDriver via SPI over RS-485 with 100' loop of CAT5.

Arduino reading the status register from the AutoDriver via SPI over RS-485 with a 100′ loop of CAT5.

In my last post, SPI over long distances, I described a method of using RS-485 to run a SPI bus over long distances. To test this setup I created two prototype shields, an Arduino SPI over RS-485 shield and an AutoDriver shield. Because the standard Arduino only has a single SPI bus and I needed two, one acting as a master and another as a slave, I would need to find a way to simulate one. Continue reading →

Share

SPI over long distances

Posted on by
5

As part of the Large Scale Delta project I needed to control multiple stepper motors, each being over a distance of roughly 50 to 150 feet. To control each motor I chose to use the Sparkfun AutoDriver board which will drive up to 3 amps continuously and communicates over SPI. The AutoDriver, which uses STmicro’s L6470 chip, has built in current limiting, over current protection, stall protection, micro stepping and more but what is most important is that it has motion commands which handle the low level motion control aspects allowing you to command a position and it will handle the rest. This along with Sparkfun’s AutoDriver Library allow for easy and precise control of a stepper motor from an Arduino. While a SPI bus is easy to use over short distances it was not designed to run more than probably a few feet and definitely not tens or hundreds of feet, when you get to that kind of distance it introduces a few issues that need to be overcome.
Continue reading →

Share

Stepper Motor Lift

Posted on by
2

Last weekend I built one rig for testing my calculations for the large scale delta project and to verify the concept. The goal was to be able to lift 22 lbs vertically using an 125 oz-in stepper motor and an AutoDriver stepper motor driver, both from SparkFun. All the mechanical bits, timing pulley, timing belt, pulley and axle, were from SPD/SI. While I was able to determine that the general concept will work it failed to lift the 22 lbs. This was due to the timing belt and pulleys not being a heavy duty enough and skipping when the load got around 8 lbs, so on the next version I will go for better a heavier duty timing pulley. See below for a video of it in action.

stepper rig 2stepper rig 1

Continue reading →

Share

Binary to Binary-Coded Decimal (BCD) Converter

Posted on by
36

A binary to binary-coded decimal, or BCD for short, is a method storing decimal numbers in binary form. The majority of the time a number in a logic design is stored as a binary number internally as to simplify math and logic operations and converted to a set of BCD numbers only when it needs to then be sent to something that requires it in decimal number form i.e. a display of some sort. The Verilog and VHDL code below is for an 8-bit binary to BCD decoder that gives and ones, tens and hundreds decimal place output for driving a display or other device. Continue reading →

Share

VHDL: Standard FIFO

Posted on by
63

FIFOs (First In, First Out) are essentially memory buffers used to temporarily store data until another process is ready to read it. As their name suggests the first byte written into a FIFO will be the first one to appear on the output. Typically FIFOs are used when you have two processes that operate and a different rate. A common example is a high speed communications channel that writes a burst of data into a FIFO and then a slower communications channel that read the data as need to send it at a slower rate.

Continue reading →

Share

VHDL: RAM

Posted on by
11

RAM is a useful thing to have when you need to store bits of information for later, the code below is for a simple, single port write first, RAM module and test bench. This may seem like a great bit of code to have lying around, but in reality it’s more for educational purposes. If you were actually going to use a RAM module like the one below you should really use a RAM generator from the manufacture of what ever device you are using ie: Xilinx, Altera, Lattice… These generated module are designed to take advantage of special RAM blocks built into the FPGA which allows them to be fast and efficient. Continue reading →

Share