VHDL: First Word Fall Through FIFO

In the Standard FIFO post I talked about how a traditional FIFO works and supplied code for one. In this post I will be describing a First Word Fall Through (FWFT) FIFO. The main difference between standard FIFOs and FWFT FIFOs are that, as the name describes, the first byte written into the FIFO immediately appears on the output (See image below). This allows the first byte to be read on the next clock cycle without having to strobe the read enable. Additionally you can read the byte and strobe the write enable high at the same time so the next byte will be available to read on the next clock cycle.
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Binary to Binary-Coded Decimal (BCD) Converter

A binary to binary-coded decimal, or BCD for short, is a method storing decimal numbers in binary form. The majority of the time a number in a logic design is stored as a binary number internally as to simplify math and logic operations and converted to a set of BCD numbers only when it needs to then be sent to something that requires it in decimal number form i.e. a display of some sort. The Verilog and VHDL code below is for an 8-bit binary to BCD decoder that gives and ones, tens and hundreds decimal place output for driving a display or other device. Continue reading

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VHDL: Standard FIFO

FIFOs (First In, First Out) are essentially memory buffers used to temporarily store data until another process is ready to read it. As their name suggests the first byte written into a FIFO will be the first one to appear on the output. Typically FIFOs are used when you have two processes that operate and a different rate. A common example is a high speed communications channel that writes a burst of data into a FIFO and then a slower communications channel that read the data as need to send it at a slower rate.

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VHDL: RAM

RAM is a useful thing to have when you need to store bits of information for later, the code below is for a simple, single port write first, RAM module and test bench. This may seem like a great bit of code to have lying around, but in reality it’s more for educational purposes. If you were actually going to use a RAM module like the one below you should really use a RAM generator from the manufacture of what ever device you are using ie: Xilinx, Altera, Lattice… These generated module are designed to take advantage of special RAM blocks built into the FPGA which allows them to be fast and efficient. Continue reading

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1’s or 0’s Counter

This little bit of code will count the number of 1’s or 0’s, depending on how it is configured, in the input signal. This module is not the most efficient way to program one of these, when it comes to synthesizing, but when dealing with variable length I/O it is the easiest. The INPUT_WIDTH variable determines how wide the input signal is and the COUNT_WIDTH does the same for the count signal. The COUNT_TYPE determines if you are counting the number of 1’s or 0’s. Every time the write enable (WrEn) is high on the rising edge of a clock pulse the module will count the number of 1’s of 0’s on the input signal and write the result to the count signal.
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VHDL: Debounce

This module is a simple debounce that will prevent switch noise from entering logic and causing havoc. It works by initially latching the input twice for synchronization between the (asynchronous) real world and the (synchronous) logic. The input is then sampled eight times, one every 50,000 clock cycles, and only after there have been eight consecutive samples of all the same reading, high or low, does the input change. This process happens continuously so whenever there in a change in the input that is steady the output will follow. With a clock of 50 MHz the samples will take place every millisecond giving a delay of 8 milliseconds, this can be adjusted for a specific time or period by changing the value of Delay. Continue reading

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Verilog: n-Bit Up Counter

This is a simple n-bit wrapping up counter. The n parameter can be changed to make this 4, 8, … bit counter were n = <number of bits> – 1. The CLK signal can be any signal you want and will increment the value of the counter on the positive edge of a pulse, RST is the negative edge reset signal which will reset the counter to 0 or any number of your choosing also be sure to change the initial value, which is the starting value when the module initialized. The output count is the current value of the counter. Continue reading

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Verilog: Dual Seven Segment Display Driver

This is an expansion upon my SevenSegmentDisplayDriver module which will allow you to drive a dual seven segment display, specifically the add-on for the Spartan 3E but it should be quite easy to modify for other FPGA’s. The basic premise of this module is you have a dual seven segment display which activates the left or right display depending on whether the enable signal is high or low. So using the code below, when the clock signal is low (right display is active) we send the lower four bits of our number to the display so they show on the right hand side display. When the clock is high (left display is active) we send the upper four bit to the left hand display. By doing this a few hundred times a second both numbers apear be on the display at once. To use this module you must slow down the clock to an appropriate rate and assign it to the enable pin for the display and the CLK input on this module. bIn in the 8-bit number you wish to display and ssOut is the array of segments for the seven segment display (See the SevenSegmentDisplayDriver post for more details) Continue reading

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Verilog: n-Bit Adder

This is code is for an simple asynchronous wrapping n-bit adder. By changing the value of n you can make it a 2, 4, … bit adder where n = <number of bits> – 1. f is the output register that will have the current value of the counter, cOut is the carry output. a & b are the number inputs and cIn is the carry input. Both the number outputs and inputs are set by the value of n so you can add two n-bit numbers and a carry bit then get an n-bit number plus carry bit out. Continue reading

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