Death by Logic

This is a simple n-bit wrapping up counter. The n parameter can be changed to make this 4, 8, … bit counter were n = <number of bits> – 1. The CLK signal can be any signal you want and will increment the value of the counter on the positive edge of a pulse, RST is the negative edge reset signal which will reset the counter to 0 or any number of your choosing also be sure to change the initial value, which is the starting value when the module initialized. The output count is the current value of the counter.

module nBitCounter(count, CLK, RST);
  parameter n = 7;

  output reg [n:0] count;
  input CLK;
  input RST;

  // Set the initial value
  initial
    count = 0;

  // Increment count on clock
  always @(posedge CLK or negedge RST)
    if (!RST)
      count = 0;
    else
      count = count + 1;

endmodule

Filed under: Computers, Programming, Software by Daniel