Verilog: n-Bit Adder

This is code is for an simple asynchronous wrapping n-bit adder. By changing the value of n you can make it a 2, 4, … bit adder where n = <number of bits> – 1. f is the output register that will have the current value of the counter, cOut is the carry output. a & b are the number inputs and cIn is the carry input. Both the number outputs and inputs are set by the value of n so you can add two n-bit numbers and a carry bit then get an n-bit number plus carry bit out.

module nBitAdder(f, cOut, a, b, cIn);
  parameter n = 7; 	

  output reg [n:0] f;
  output reg cOut;
  input [n:0] a;
  input [n:0] b;
  input cIn;

  always @(a, b, cIn)
    {cOut, f} = a + b + cIn;
endmodule

One Response to “Verilog: n-Bit Adder”

  1. thank you

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