In the Standard FIFO post I talked about how a traditional FIFO works and supplied code for one. In this post I will be describing a First Word Fall Through (FWFT) FIFO. The main difference between standard FIFOs and FWFT FIFOs are that, as the name describes, the first byte written into the FIFO immediately appears on the output (See image below). This allows the first byte to be read on the next clock cycle without having to strobe the read enable. Additionally you can read the byte and strobe the write enable high at the same time so the next byte will be available to read on the next clock cycle.
As with the standard FIFO the FWFT FIFO module below have two settings that can be configured to adjust the width and depth of the FIFO. The DATA_WIDTH variable adjusts the size of the DataIn and DataOut buses so that you can write different sizes of bytes if needed. The FIFO_DEPTH variable adjusts how big the internal memory of the FIFO is.
In order to write data into the FIFO first push the data onto the DataIn bus and then strobe the WriteEn input high for one clock cycle. This will write whatever is on DataIn into the FIFOs internal memory. If writing in bulk the WriteEn signal can be left high while changing the data on the DataIn bus each clock cycle. When the Full flag goes high, this means that the FIFO’s memory is full and will not accept any more writes until data is read using the ReadEn input. If data is written while the Full flag is high it will be ignored.
First word fall through timing example, with 0x01 being the first word written into a FIFO.
For a FWFT FIFO once the first byte is written into the FIFO it will immediately appear on the DataOut bus. Allowing you to read the first byte without pulsing the ReadEn signal first, this feature is the defining characteristic of a FWFT FIFO. Once a byte has been written into the FIFO the Empty flag will go low. To read the next byte from the FWFT FIFO strobe the ReadEn signal high for one clock cycle. If there is no more data to read from the FIFO the DataOut bus will become invalid data and the Empty flag will go high.
First word fall through timing example, with 0x40 being the last valid word read from a FIFO.
VHDL Code
https://github.com/DeathByLogic/HDL/blob/master/FIFO/Standard%20FIFO/STD_FIFO.vhd
Test bench
Very nice, short and sweet. I’ve coded my own before but I like yours better, mind if I put it in my design? It’s for my own personal use anyway!
Thanks
Feel free to use any code here as you wish, there is no copyright or restrictions.
Thank you! Very useful post!
Could you explain to me one thing:
when you code
“– Update data output
DataOut <= Memory(Tail);"
you put this in Rising_Edge(clk) section of the process. I see in simulate:
when I set readen signal to '1', the counter Tail has incremented on the rising clk, but why DataOut changes without rising clk on the next cycle of clk?
Also, in RTL we see FDE trigger after the memory – how does it works? I think, we need two clocks to change Tail counter and then to change DataOut memory.
Thanks a lot.
The head and tail are variables, which act more like software variables in that they are updated instantly so you don’t have to wait for the next clock edge. So when the data output is updated tail has already been updated by the read and write operations above.
In my design I need to have 2 different clocks, rd_clk and wr_clk to a FWFT FIFO with 8-bit bus_in bus_out . The wr_clk (18Mhz) is faster than rd_clk (16Mhz). I generated the Xilinx FIFO core but the read DataOut is missing bytes occasionally but persistently. Please give me any idea why the data is missing occasionally at the dout.
Read1stFIFOInst: entity work.ReadFIFOv4
port map (
rst => RAMRST,
wr_clk => Clk18MHz,
rd_clk => Clk16MHz,
wr_en => Write_En,
din => Write_Data,
rd_en => Read_Enable,
dout => Read_Data,
empty => Flag_Empty,
almost_full => open,
Prog_full => open,
full => Flag_Full );
Write_Enable < = Connection and not Flag_Full; — Connection always ='1'
Read_enable <= Connection and not Flag_Empty; — Connection always ='1'
Thanks very much
Reading does not have time to select data and part is lost, which follows from rd_clk less wr_clk.
Use the x16 data bus for reading.
Or use two FIFO x8, in the first FIFO write every odd clock wr_clk, in the second FIFO every even clock.
how will the valid be handled in FWFT FIFO.?
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https://drive.google.com/file/d/178b95HuevXj8TVpIGX8zACEtlw9FkMBL/preview
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where I get the verilog code for this.
thank you!