VHDL: Debounce

This module is a simple debounce that will prevent switch noise from entering logic and causing havoc. It works by initially latching the input twice for synchronization between the (asynchronous) real world and the (synchronous) logic. The input is then sampled eight times, one every 50,000 clock cycles, and only after there have been eight consecutive samples of all the same reading, high or low, does the input change. This process happens continuously so whenever there in a change in the input that is steady the output will follow. With a clock of 50 MHz the samples will take place every millisecond giving a delay of 8 milliseconds, this can be adjusted for a specific time or period by changing the value of Delay.

Change Log

3/3/2010: Updated code so that output would be registered rather than combinational.

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12 thoughts on “VHDL: Debounce

  1. I am new to VHDL programming and ran across this website regarding debouncing inputs. This code was done very nicely and easy to follow, great job. I do have one question. Lines 25 and 26 when you double latch the input signal. I would presume the order of the lines would be reversed. Instead of:

    DPB <= SPB;
    SPB <= x;

    it would be

    SPB <=x;
    DPB <=SPB;

    Am I missing something? Thanks for any feedback. Again I am new to VHDL programming.

    • Pete, because this hardware and everything happens simultaneously on the rising edge of the clock, all the operations happen at the same time so it does not really matter what order they are in.

  2. ok, thanks so much for the response Daniel. I kind of had that in the back of my mind but was not sure. Definitely a different type of programming mentality in VHDL versus programming software. Thank you again.

  3. I am using a logic board that has 12 inputs (8 switches and 4 buttons).

    I added this debouncer for all of the inputs, and it ends up using over 50% of the available slice resources!

    Unfortunately, this takes up more than I have available on the board after everything else (simple 8 bit computer).

    • I changed the default mapping optimization to add extra effort and “continue on impossible”.

      Seems to have addressed the resource overmap issue.

  4. Excellent VHDL my friend. Worked brilliantly in a University project, used on the Xilinx Nexys 3 FPGA Development Board momentary push buttons. Many thanks.

    • “6 downto 0” is correct. The DReg being assigned to is an 8-bit signal, we are taking the lower 7 bits (6 downto 0) of DReg and the 1 bit signal DPB and combining them into an 8-bit signal with the “&” operator.

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