This is a simple n-bit wrapping up counter. The n parameter can be changed to make this 4, 8, … bit counter were n = <number of bits> – 1. The CLK signal can be any signal you want and will increment the value of the counter on the positive edge of a pulse, RST is the negative edge reset signal which will reset the counter to 0 or any number of your choosing also be sure to change the initial value, which is the starting value when the module initialized. The output count is the current value of the counter.
Code
Verilog
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module nBitCounter(count, clk, rst_n); parameter n = 7; output reg [n:0] count; input clk; input rst_n; // Set the initial value initial count = 0; // Increment count on clock always @(posedge clk or negedge rst_n) if (!rst_n) count = 0; else count = count + 1; endmodule |
Test Bench
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module nBitCounter_TB; // Inputs reg clk; reg rst_n; // Outputs wire [7:0] count; // Instantiate the Unit Under Test (UUT) nBitCounter uut ( .count(count), .clk(clk), .rst_n(rst_n) ); initial begin // Initialize Inputs clk = 0; rst_n = 1; // Force Reset after delay #20 rst_n = 0; #25 rst_n = 1; end // Generate clock always #1 clk = !clk; endmodule |
Change Log
12/28/2013: Update signals names to better represent function; Added test bench.
i donot know how to generate waveforms by using verilog test bunch . could you please post code for that
Any particular type of waveform you are trying to create?
please post more details about counters types and their circuit diagram ,woking, timing diagaram
please send me testbench of this code (Verilog: n-Bit Up Counter) at aliraza1150@live.com
or post it in comment box…
i can not write it
i am using Model sim simulation softwere to impliment Verilog: n-Bit Up Counter