Verilog: n-Bit Up Counter

This is a simple n-bit wrapping up counter. The n parameter can be changed to make this 4, 8, … bit counter were n = <number of bits> – 1. The CLK signal can be any signal you want and will increment the value of the counter on the positive edge of a pulse, RST is the negative edge reset signal which will reset the counter to 0 or any number of your choosing also be sure to change the initial value, which is the starting value when the module initialized. The output count is the current value of the counter.



Test Bench

 Change Log

12/28/2013: Update signals names to better represent function; Added test bench.


9 thoughts on “Verilog: n-Bit Up Counter

  1. I want to generate a waveform from clock pulse so that it is high only at the first clock pulse and low at the rest…
    I wanted to do it using counter. Facing some issues in it. Any suggestions?
    Also can it be done by any other method?

    P.S. Thankyou

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